VSD SoC Design of the PicoRV32 RISCV micro-processor

VSD – SoC Design of the PicoRV32 RISCV micro-processor, available at $44.99, has an average rating of 3.6, with 28 lectures, based on 63 reviews, and has 657 subscribers.

You will learn about Run a full physical design flow from RTL design to GDSII, making it ready for tape-out. For freshers, this course will make them industry ready and might increase their chances of getting placed or work for tier-1 company For experienced VLSI Physical design professionals, this will give a bigger picture of SoC physical design, which is appplication specific For senior non-VLSI engineers, this course will help them understand the whole flow, with pictures, labs and visualization This course is ideal for individuals who are Anyone curious to know end-to-end aspects of chip designing i.e from SOC design to tapeout, which involves lot of steps like placement, routing, clock tree synthesis, DRC cleanup, LVS fixing or Anyone curious to know how to achieve all of above using all EDA open-source tools. Not a single penny to be paid as license fee or Anyone who wishes to innovate, implement and submit a paper on any design, implemented using open-source tools It is particularly useful for Anyone curious to know end-to-end aspects of chip designing i.e from SOC design to tapeout, which involves lot of steps like placement, routing, clock tree synthesis, DRC cleanup, LVS fixing or Anyone curious to know how to achieve all of above using all EDA open-source tools. Not a single penny to be paid as license fee or Anyone who wishes to innovate, implement and submit a paper on any design, implemented using open-source tools.

Enroll now: VSD – SoC Design of the PicoRV32 RISCV micro-processor

Summary

Title: VSD – SoC Design of the PicoRV32 RISCV micro-processor

Price: $44.99

Average Rating: 3.6

Number of Lectures: 28

Number of Published Lectures: 28

Number of Curriculum Items: 28

Number of Published Curriculum Objects: 28

Original Price: $189.99

Quality Status: approved

Status: Live

What You Will Learn

Run a full physical design flow from RTL design to GDSII, making it ready for tape-out.

For freshers, this course will make them industry ready and might increase their chances of getting placed or work for tier-1 company

For experienced VLSI Physical design professionals, this will give a bigger picture of SoC physical design, which is appplication specific

For senior non-VLSI engineers, this course will help them understand the whole flow, with pictures, labs and visualization

Who Should Attend

Anyone curious to know end-to-end aspects of chip designing i.e from SOC design to tapeout, which involves lot of steps like placement, routing, clock tree synthesis, DRC cleanup, LVS fixing

Anyone curious to know how to achieve all of above using all EDA open-source tools. Not a single penny to be paid as license fee

Anyone who wishes to innovate, implement and submit a paper on any design, implemented using open-source tools

Target Audiences

Anyone curious to know end-to-end aspects of chip designing i.e from SOC design to tapeout, which involves lot of steps like placement, routing, clock tree synthesis, DRC cleanup, LVS fixing

Anyone curious to know how to achieve all of above using all EDA open-source tools. Not a single penny to be paid as license fee

Anyone who wishes to innovate, implement and submit a paper on any design, implemented using open-source tools

This webinar was conducted on 2nd June 2018

After successful webinar on Making of Raven Chip, this time we take the chip forward and implement using end-to-end opensource EDA tools, and all on efabless cloud. What does this mean to us? It means, you can start innovating on a design, build RTL and do synth/PD/LVS/DRC all using opensource EDA framework and not pay a single penny for license.

The big question How is this possible? Thereby, I welcome you all to my next (follow-up) webinar with Tim Edwards and Mohamed Kassem

About instructors –

Tim Edwards

Tim Edwards has been
doing analog VLSI design and collecting and developing open-source EDA
tools for over 25 years.? He has worked for the Johns Hopkins Applied Physics Lab, startups MultiGiG (bought by Analog Devices) and most recently, eFabless.?

Mohamed Kassem

Mohamed
Kassem is the cofounder and CTO of eFabless corporation. Prior to
launching eFabless in 2014, Mohamed held several technical and global
leadership positions within TI’s Wireless Business Unit. He
joined TI in 2000 at the beginning of the digital telephony revolution
fueled by the unprecedented integration of major phone functions on a
single SoC. He led the first development of 45nm, 28nm analog & mixed-signal IP functions for wireless applications processors. Mohamed holds a masters degree in electrical engineering from the University of Waterloo, Ontario, Canada.

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction to webinar

Lecture 2: Introduction to VSDOpen conference

Chapter 2: efabless interactive tutorial

Lecture 1: Introduction to webinar and SPI design selection for physical design

Lecture 2: Introduction to efabless platform and webinar agenda

Lecture 3: LIVE QnA with participants and steps to login to efabless marketplace

Chapter 3: CloudV interactive tutorial

Lecture 1: Introduction to CloudV application

Lecture 2: Steps to synthesize to target process and export to open-galaxy

Lecture 3: Steps to import synthesized netlist into open-galaxy

Chapter 4: Synthesis flow interactive tutorial

Lecture 1: Steps to start synthesis flow tool and run synthesis

Lecture 2: Pin arrangement UI and automatic grouping of vectors

Lecture 3: Few tips on pin-placement and floor-planning chip

Lecture 4: LIVE QnA with participants regarding pacement and STA

Lecture 5: Routing post-route STA and LVS check

Chapter 5: LVS & DRC

Lecture 1: Steps to fix LVS, Magic short-cut keys and run DRC

Lecture 2: LIVE QnA with participants on LVS and steps to fix DRC

Lecture 3: DRC cleaning steps LIVE and QnA with partcipants on DRC

Lecture 4: LIVE QnA with participants about future of qflow and efabless

Chapter 6: Full chip integration in open-galaxy

Lecture 1: Steps to create a new project for floorplanning and integration

Lecture 2: Steps to populate layout from library manager and select SPI block

Lecture 3: Steps to select, generate copies and arrange pad frames

Lecture 4: Steps to abut pads and ensure pad-frame is DRC clean

Chapter 7: Signal routing

Lecture 1: reset signal routing steps

Lecture 2: sck, csb, other signal routing and DRC clean step

Lecture 3: Dynamic power estimation and power routing

Lecture 4: Tie-down unused inputs, add substrate contacts and antenna diodes

Lecture 5: Add pin labels, review completed layout and final LVS check

Chapter 8: Challenge & Conclusion

Lecture 1: Challenge description and mode of submission

Lecture 2: Conclusion

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

Tim Edwards
Analog VLSI Design and CAD tools

Rating Distribution

1 stars: 3 votes

2 stars: 4 votes

3 stars: 14 votes

4 stars: 18 votes

5 stars: 24 votes

Frequently Asked Questions

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